1. Field of the Invention
The present invention relates to a power semiconductor device and an operation method thereof.
2. Description of Related Art
A power semiconductor device for supplying power to a load is known. For example, a power semiconductor device called IPD (Intelligent Power Device) is used in an electronic control system of a vehicle and controls electric power supply to a headlight and the like in accordance with an instruction from a microcomputer. In such a power semiconductor device, a high-side switch is typically used (for example, refer to Patent Literature 1 (Japan Patent Publication JP-H06-97375) and Patent Literature 2 (Japan Patent Publication JP-2002-290221)).
FIG. 1 shows a configuration of a power semiconductor device described in Patent Literature 1. The power semiconductor device has a power-supply terminal TV, an input terminal TI, an output terminal TO, an output transistor 10 and a gate charge-discharge circuit 30. A power-supply voltage VDD is supplied to the power-supply terminal TV. A power-ON signal PWR is supplied to the input terminal TI. In response to activation of the power-ON signal PWR, the power semiconductor device outputs power from the output terminal TO.
The output transistor 10 is connected between the power-supply terminal TV and the output terminal TO. More specifically, the output transistor 10 is an N-channel MOSFET and its gate, drain and source are respectively connected to a node ND, the power-supply terminal TV and the output terminal TO. The output terminal TO is connected to one end of a load 20, and the other end of the load 20 is connected to a ground terminal TG. In this manner, the output transistor 10 is so connected as to function as a high-side switch.
The gate charge-discharge circuit 30 charges and discharges the node ND and thereby ON/OFF controls the output transistor 10. More specifically, the gate charge-discharge circuit 30 has a control input circuit 31, a booster circuit 32, a discharge transistor (discharge switch) 33 and diodes 34 and 35. The control input circuit 31 controls the booster circuit 32 and the discharge transistor 33 depending on the power-ON signal PWR. The booster circuit 32 charges the node ND to a high voltage higher than the power-supply voltage VDD. The discharge transistor 33 is an N-channel MOSFET and its gate, back gate, source and drain are respectively connected to a node NA, a node NB, a node NC and the node ND. An anode and a cathode of the diode 34 are respectively connected to the node NC and a ground terminal. An anode and a cathode of the diode 35 are respectively connected to the node NC and the output terminal TO.
When the power-ON signal PWR is activated, the control input circuit 31 activates the booster circuit 32 and also supplies a Low-level signal to the node NA to turn OFF the discharge transistor 33. The booster circuit 32 charges the node ND to the high voltage higher than the power-supply voltage VDD. As a result, the output transistor 10 is turned ON and power is supplied to the load 20.
When the power-ON signal PWR is deactivated, the control input circuit 31 deactivates the booster circuit 32 and also supplies a High-level signal to the node NA. Thus, the booster circuit 32 stops operation and the discharge transistor 33 is turned ON. As a result, the node ND is discharged and the output transistor 10 is turned OFF. It should be noted that when a voltage of the node ND becomes a voltage that is higher than the ground voltage GND by a forward voltage drop (VF) of the diode 34 or the diode 35, the discharging through the discharge transistor 33 stops.